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Final Electrical Specifications
LTC1657L Parallel 16-Bit Rail-to-Rail Micropower DAC
FEATURES
s s s s s s s s s s s s s
DESCRIPTION
April 2000
16-Bit Monotonic Over Temperature 3V Single Supply Operation Deglitched Rail-to-Rail Voltage Output: 8nV * s ICC: 650A Typ Maximum DNL Error: 1LSB Settling Time: 20s to 1LSB Internal or External Reference Internal Power-On Reset to 0V Asynchronous CLR Pin Output Buffer Configurable for Gain of 1 or 2 Parallel 16-Bit or 2-Byte Double Buffered Interface Narrow 28-Lead SSOP Package 5V Version Available (LTC1657)
The LTC(R)1657L is a complete single supply, rail-to-rail voltage output, 16-bit digital-to-analog converter (DAC) in a 28-pin SSOP or PDIP package. It includes a rail-to-rail output buffer amplifier, an internal 1.25V reference and a double buffered parallel digital interface. The LTC1657L operates from a 2.7V to 5.5V supply. It has a separate reference input pin that can be driven by an external reference. The full-scale output can be 1 or 2 times the reference voltage depending on how the X1/X2 pin is connected. The LTC1657L is similar to Linear Technology Corporation's LTC1450 12-bit VOUT DAC family allowing an easy upgrade path. It is the only buffered 16-bit parallel DAC in a 28-lead SSOP package and includes an onboard reference for stand alone performance.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIONS
s s s s
Instrumentation Industrial Process Control Automatic Test Equipment Communication Test Equipment
BLOCK DIAGRA
19 D15 (MSB) 18 17 16 15 14 13 12 DATA IN FROM MICROPROCESSOR DATA BUS D8 11 D7 10 9 8 7 6 5 4 D0 (LSB) 3 CSMSB FROM MICROPROCESSOR DECODE LOGIC 1 WR 2 CSLSB 28 LDAC FROM SYSTEM RESET 27 CLR
2.7V TO 5.5V 23 REFOUT REFERENCE 1.25V MSB 8-BIT INPUT REGISTER
1.0
22 REFHI
24 VCC
16-BIT DAC REGISTER
16-BIT DAC
+ -
VOUT
25 0V TO 2.5V
DNL ERROR (LSB)
LSB 8-BIT INPUT REGISTER
R R
POWER-ON RESET GND 20 REFLO 21 X1/X2 26
1657 TA01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Differential Nonlinearity vs Input Code
0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 - 1.0 0 16484 32768 CODE 49152 65535
1657 TA02
1
LTC1657L
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW WR CSLSB CSMSB (LSB) D0 D1 D2 D3 D4 D5 1 2 3 4 5 6 7 8 9 28 LDAC 27 CLR 26 X1/X2 25 VOUT 24 VCC 23 REFOUT 22 REFHI 21 REFLO 20 GND 19 D15 (MSB) 18 D14 17 D13 16 D12 15 D11 GN PACKAGE 28-LEAD PLASTIC SSOP
VCC to GND .............................................. - 0.5V to 7.5V TTL Input Voltage, REFHI, REFLO, X1/X2 .......................... - 0.5V to 7.5V VOUT, REFOUT ............................ - 0.5V to (VCC + 0.5V) Operating Temperature Range LTC1657LC ............................................. 0C to 70C LTC1657LI ......................................... - 40C to 85C Maximum Junction Temperature .......................... 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1657LCGN LTC1657LCN LTC1657LIGN LTC1657LIN
D6 10 D7 11 D8 12 D9 13 D10 14 N PACKAGE 28-LEAD PDIP
TJMAX = 125C, JA = 95C/ W (G) TJMAX = 125C, JA = 58C/ W (N)
Consult factory for Military grade parts.
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded, REFOUT tied to REFHI, REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.
SYMBOL PARAMETER Resolution Monotonicity DNL INL ZSE VOS VOSTC Differential Nonlinearity Integral Nonlinearity Zero Scale Error Offset Error Offset Error Tempco Gain Error Gain Error Drift Power Supply VCC ICC Positive Supply Voltage Supply Current Short-Circuit Current Low Short-Circuit Current High Output Impedance to GND Output Line Regulation For Specified Performance 2.7V VCC 5.5V (Note 4) VOUT Shorted to GND VOUT Shorted to VCC Input Code = 0 Input Code = 65535, VCC = 2.7V to 5.5V
q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN
q q
TYP
MAX
UNITS Bits Bits
DAC (Note 2) 16 16 0.5 4 0 0.3 5 2 1 2.7 650 60 70 120 5.5 1200 120 140 275 3 16 1.0 12 2 4
Guaranteed Monotonic (Note 3) (Note 3) Measured at Code 200
q q q q
V/C LSB ppm/C V A mA mA mV/V
Op Amp DC Performance
q q q q
2
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WW
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LSB LSB mV mV
LTC1657L
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded, REFOUT tied to REFHI, REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.
SYMBOL PARAMETER Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Midscale Glitch Impulse Output Voltage Noise Spectral Density Digital I/O (VCC = 3V) VIH VIL ILEAK CIN tCS tWR tCWS tCWH tDWS tDWH tLDAC tCLR Digital Input High Voltage Digital Input Low Voltage Digital Input Leakage Digital Input Capacitance CS (MSB or LSB) Pulse Width WR Pulse Width CS to WR Setup CS to WR Hold Data Valid to WR Setup Data Valid to WR Hold LDAC Pulse Width CLR Pulse Width Reference Output Voltage Reference Output Temperature Coefficient Reference Line Regulation Reference Load Regulation Short-Circuit Current Reference Input REFHI, REFLO Input Range (Note 6) See Applications Information X1/X2 Tied to VOUT X1/X2 Tied to GND
q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS (Note 5)
MIN
q
TYP 0.7 20 10 0.3
MAX
UNITS V/s s s nV*s nV*s nV/Hz
AC Performance 0.3 (Note 5) to 0.0015% (16-Bit Settling Time) (Note 5) to 0.012% (13-Bit Settling Time)
DAC Switch Between 8000H and 7FFFH At 1kHz
8 200
2.0 0.6 10 10
V V A pF ns ns ns ns ns ns ns ns 1.25 15 1.26 V ppm/C 1 3 50 100 mV/V mV/A mA
VIN = GND to VCC (Note 6)
q
Switching Characteristics (VCC = 3V)
q q q q q q q q
60 60 0 0 60 0 60 60 1.24
Reference Output (REFOUT)
q
VCC = 2.7V to 5.5V Measured at IOUT = 100A REFOUT Shorted to GND
q q q
0 0 16 23
VCC - 1.5 VCC /2
V k
REFHI Input Resistance Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: External reference REFHI = 1.3V, VCC = 3V Note 3: Nonlinearity is defined from code 128 to code 65535 (full scale). See Applications Information.
Note 4: Digital inputs at 0V or VCC. Note 5: DAC switched between all 1s all 0s, slew rate is measured from 0.8V to 2V. VCC =3V. Note 6: Guaranteed by design. Not subject to test.
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LTC1657L
PIN FUNCTIONS
WR (Pin 1): Write Input (Active Low). Used with CSMSB and/or CSLSB to control the input registers. While WR and CSMSB and/or CSLSB are held low, data writes into the input register. CSLSB (Pin 2): Chip Select Least Significant Byte (Active Low). Used with WR to control the LSB 8-bit input registers. While WR and CSLSB are held low, the LSB byte writes into the LSB input register. Can be connected to CSMSB for simultaneous loading of both sets of input latches on a 16-bit bus. CSMSB (Pin 3): Chip Select Most Significant Byte (Active Low). Used with WR to control the MSB 8-bit input registers. While WR and CSMSB are held low, the MSB byte writes into the MSB input register. Can be connected to CSLSB for simultaneous loading of both sets of input latches on a 16-bit bus. D0 to D7 (Pins 4 to 11): Input data for the Least Significant Byte. Written into LSB input register when WR = 0 and CSLSB = 0. D8 to D15 (Pins 12 to 19): Input data for the Most Significant Byte. Written into MSB input register when WR = 0 and CSMSB = 0. GND (Pin 20): Ground. REFLO (Pin 21): Lower input terminal of the DAC's internal resistor ladder. Typically connected to Analog Ground. An input code of (0000)H will connect the positive input of the output buffer to this end of the ladder. Can be used to offset the zero scale above ground. REFHI (Pin 22): Upper input terminal of the DAC's internal resistor ladder. Typically connected to REFOUT. An input code of (FFFF)H will connect the positive input of the output buffer to 1LSB below this voltage. REFOUT (Pin 23): Output of the internal 1.25V reference. Typically connected to REFHI to drive internal DAC resistor ladder. VCC (Pin 24): Positive Power Supply Input. 2.7V VCC 5.5V. Requires a 0.1F bypass capacitor to ground. VOUT (Pin 25): Buffered DAC Output. X1/X2 (Pin 26): Gain Setting Resistor Pin. Connect to GND for G = 2 or to VOUT for G = 1. This pin should always be tied to a low impedance source, such as ground or VOUT, to ensure stability of the output buffer when driving capacitive loads. CLR (Pin 27): Clear Input (Asynchronous Active Low). A low on this pin asynchronously resets all input and DAC registers to 0s. LDAC (Pin 28): Load DAC (Asynchronous Active Low). Used to asynchronously transfer the contents of the input registers to the DAC register which updates the output voltage. If held low, the DAC register loads data from the input registers which will immediately update VOUT.
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LTC1657L
DIGITAL INTERFACE TRUTH TABLE
CLR L H H H H H H H H H CSMSB X X X L H L X H X L CSLSB X X X H L L X X H L WR X X X L L L H X X L LDAC X L H X X X X X X L FUNCTION Clears input and DAC registers to zero Loads DAC register with contents of input registers Freezes contents of DAC register Writes MSB byte into MSB input register Writes LSB byte into LSB input register Writes MSB and LSB bytes into MSB and LSB input registers Inhibits write to MSB and LSB input registers Inhibits write to MSB input register Inhibits write to LSB input register Data bus flows directly through input and DAC registers
TIMING DIAGRAM
CSLSB
CSMSB t CWS WR t LDAC LDAC t DWS DATA DATA VALID DATA VALID
1657 TD
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UW
t CS
t CS
t WR
t CWH t WR
t DWH DAC UPDATE
5
LTC1657L
DEFI ITIO S
Resolution (n): Resolution is defined as the number of digital input bits (n). It defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Full-Scale Voltage (VFS): This is the output of the DAC when all bits are set to 1. Voltage Offset Error (VOS): Normally, the DAC offset is the voltage at the output when the DAC is loaded with all zeros. The DAC can have a true negative offset, but because the part is operated from a single supply, the output cannot go below zero. If the offset is negative, the output will remain near 0V resulting in the transfer curve shown in Figure 1.
OUTPUT VOLTAGE
NEGATIVE OFFSET
Figure 1. Effect of Negative Offset
The offset of the part is measured at the code that corresponds to the maximum offset specification: VOS = VOUT - [(Code)(VFS)/(2n - 1)] Least Significant Bit (LSB): One LSB is the ideal voltage difference between two successive codes. LSB = (VFS - VOS)/(2n - 1) = (VFS - VOS)/65535 Nominal LSBs: LTC1657L LSB = 2.5V/65535 = 38.1V DAC Transfer Characteristic:
REFHI - REFLO VOUT = G * CODE + REFLO 65536
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G = 1 for X1/X2 connected to VOUT G = 2 for X1/X2 connected to GND CODE = Decimal equivalent of digital input (0 CODE 65535) Zero-Scale Error (ZSE): The output voltage when the DAC is loaded with all zeros. Since this is a single supply part, this value cannot be less than 0V. Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the end points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below zero, the linearity is measured between full scale and the code corresponding to the maximum offset specification. The INL error at a given input code is calculated as follows: INL (In LSBs) = [VOUT - VOS - (VFS - VOS) (code/65535)]
0V
DAC CODE
1657 F01
VOUT = The output voltage of the DAC measured at the given input code Differential Nonlinearity (DNL): DNL is the difference between the measured change and the ideal one LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (VOUT - LSB)/LSB VOUT = The measured voltage difference between two adjacent codes Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in nV * s.
(
)
LTC1657L
OPERATION
Parallel Interface The data on the input of the DAC is written into the DAC's input registers when Chip Select (CSLSB and/or CSMSB) and WR are at a logic low. The data that is written into the input registers will depend on which of the Chip Selects are at a logic low (see Digital Interface Truth Table). If WR and CSLSB are both low and CSMSB is high, then only data on the eight LSBs (D0 to D7) is written into the input registers. Similarly, if WR and CSMSB are both low and CSLSB is high, then only data on the eight MSBs (D8 to D15) is written into the input registers. Data is written into both the Least Significant Data Bits (D0 to D7) and the Most Significant Bits (D8 to D15) at the same time if WR, CSLSB and CSMSB are low. If WR is high or both CSMSB and CSLSB are high, then no data is written into the input registers. Once data is written into the input registers, it can be written into the DAC register. This will update the analog voltage output of the DAC. The DAC register is written by a logic low on LDAC. The data in the DAC register will be held when LDAC is high. When WR, CSLSB, CSMSB and LDAC are all low, the registers are transparent and data on pins D0 to D15 flows directly into the DAC register. For an 8-bit data bus connection, tie the MSB byte data pins to their corresponding LSB byte pins (D15 to D7, D14 to D6, etc). Power-On Reset The LTC1657L has an internal power-on reset that resets all internal registers to 0's on power-up (equivalent to the CLR pin function). Reference The LTC1657L includes an internal 1.25V reference, giving the LTC1657L a full-scale range of 2.5V in the gain-of2 configuration. The onboard reference in the LTC1657L is not internally connected to the DAC's reference resistor string but is provided on an adjacent pin for flexibility. Because the internal reference is not internally connected to the DAC resistor ladder, an external reference can be used or the resistor ladder can be driven by an external source in multiplying applications. The external reference or source must be capable of driving the 16k (minimum) DAC ladder resistance. Internal reference output voltage noise spectral density can be reduced with a bypass capacitor to ground. (Note: The reference does not require a bypass capacitor to ground for nominal operation.) When bypassing the reference, a small value resistor in series with the capacitor is recommended to help reduce peaking on the output. A 10 resistor in series with a 4.7F capacitor is optimum for reducing reference generated noise. Internal reference output noise at 1kHz is typically 80nV/Hz. DAC Resistor Ladder The high and low end of the DAC ladder resistor string (REFHI and REFLO, respectively) are not connected internally on this part. Typically, REFHI will be connected to REFOUT and REFLO will be connected to GND. X1/X2 connected to GND will give the LTC1657L a full-scale output swing of 2.5V. Either of these pins can be driven up to VCC - 1.5V when using the buffer in the gain-of-1 configuration. The resistor string pins can be driven to VCC/2 when the buffer is in the gain of 2 configuration. The resistance between these two pins is typically 30k (16k min). Voltage Output The output buffer for the LTC1657L can be configured for two different gain settings. By tying the X1/X2 pin to GND, the gain is set to 2. By tying the X1/X2 pin to VOUT, the gain is set to unity. The LTC1657L rail-to-rail buffered output can source or sink 5mA to within 500mV of the positive supply voltage or ground at room temperature. The output stage is equipped with a deglitcher that results in a midscale glitch impulse of 8nV * s. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 40 when driving a load to the rails.
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LTC1657L
APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 1b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC /2. If VREF = VCC /2 and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 1c. No full-scale limiting can occur if VREF is less than (VCC - FSE)/2. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
VCC
OUTPUT VOLTAGE
0
OUTPUT VOLTAGE
0V NEGATIVE OFFSET INPUT CODE (b)
1657 F02
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC /2
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VCC
POSITIVE FSE
VREF = VCC /2
OUTPUT VOLTAGE
INPUT CODE (c)
VREF = VCC /2
32768 INPUT CODE (a)
65535
LTC1657L
TYPICAL APPLICATION
This circuit shows how to measure negative offset. Since LTC1657L operates on a single supply, if its offset is negative, the output for code 0 limits at 0V. To measure this negative offset, a negative supply is needed. Connect resister R1 as shown in the figure, the output voltage is the offset when code 0 is loaded in.
3V
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P
5:19 2 3 1 28 27
22 23 REFHI REFOUT
24 VCC
0.1F
DATA 10:15 CSLSB CSMSB LTC1657L WR LDAC CLR GND X1/X2 REFLO 26 21 20
VOUT
25 R1 100k -3V
1657 TA03
9
LTC1657L
PACKAGE DESCRIPTION
0.015 0.004 x 45 (0.38 0.10) 0.0075 - 0.0098 (0.191 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP
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Dimensions in inches (millimeters) unless otherwise noted. GN Package 28-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.386 - 0.393* (9.804 - 9.982) 28 27 26 25 24 23 22 21 20 19 18 17 1615
0.033 (0.838) REF
0.229 - 0.244 (5.817 - 6.198)
0.150 - 0.157** (3.810 - 3.988)
1 0.053 - 0.069 (1.351 - 1.748)
23
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56
7
8
9 10 11 12 13 14 0.004 - 0.009 (0.102 - 0.249)
0.008 - 0.012 (0.203 - 0.305)
0.0250 (0.635) BSC
GN28 (SSOP) 1098
LTC1657L
PACKAGE DESCRIPTION
0.255 0.015* (6.477 0.381)
0.300 - 0.325 (7.620 - 8.255)
0.020 (0.508) MIN 0.009 - 0.015 (0.229 - 0.381)
(
+0.035 0.325 -0.015 +0.889 8.255 -0.381
)
0.125 (3.175) MIN
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
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Dimensions in inches (millimeters) unless otherwise noted. N Package 28-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.370* (34.789) MAX 28 27 26 25 24 23 22 21 20 19 18 17 16 15
1 0.130 0.005 (3.302 0.127)
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3
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14
0.045 - 0.065 (1.143 - 1.651)
0.065 (1.651) TYP 0.018 0.003 (0.457 0.076)
0.005 (0.127) MIN
0.100 (2.54) BSC
N28 1098
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LTC1657L
RELATED PARTS
PART NUMBER LTC1446(L) LTC1450(L) LTC1458(L) LTC1650 LTC1655(L) LTC1657 DESCRIPTION Dual 12-Bit VOUT DACs in SO-8 Package Single 12-Bit VOUT DACs with Parallel Interface Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Single 16-Bit VOUT Industrial DAC in 16-Pin SO Single 16-Bit VOUT DAC with Serial Interface in SO-8 Single 16-Bit VOUT DAC with Parallel Interface COMMENTS VCC = 5V (3V), VOUT = 0V to 4.095V (0V to 2.5V) VCC = 5V (3V), VOUT = 0V to 4.095V (0V to 2.5V) VCC = 5V (3V), VOUT = 0V to 4.095V (0V to 2.5V) VCC = 5V, Low Power, Deglitched, 4-Quadrant Multiplying VOUT VCC = 5V (3V), Low Power, Deglitched, VOUT = 0V to 4.096V (0V to 2.5V) VCC = 5V, Low Power, Deglitched, VOUT = 0V to 4.096V with Internal Reference
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
1657Li LT/TP 0400 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2000

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